Dec.17_15:30_AIの未来を支える半導体インフラの革新

As companies step up efforts to capture AI-powered business opportunities, big ambitions are riding on cutting-edge, nanoscale semiconductors. But as global production and resource bottlenecks persist, there aren’t enough advanced AI chips to go around. How is this chip shortage impacting buyers and suppliers? A new report from the IBM Institute for Business Value, in partnership with SEMI, indicates that an already constrained AI semiconductor market is about to get even tighter.

This talk explores how advanced packaging can simultaneously break the AI “memory wall” and make semiconductor manufacturing more sustainable. As GPUs and AI accelerators increasingly sit idle waiting for data, performance and energy efficiency are now constrained less by transistors and more by how we connect logic to HBM-class memory. I’ll compare today’s CoWoS + HBM paradigm—high-resolution interposers, extreme process complexity, and a single-region capacity bottleneck—with emerging High-Resolution Interconnect (HRI) approaches that rethink how fine-pitch RDLs and micro-bumps are made. Using Syenta’s Localized Electrochemical Manufacturing (LEM) as a case study, I’ll show how stamp-based, additive copper patterning can replicate 1 µm features, collapse up to 60–70% of semi-additive and dual-damascene process steps, cut per-layer costs by ~50–70%, and reduce energy consumption by up to ~100× at the wafer level. This enables higher I/O density for AI packages while slashing materials, chemicals, and floor-space requirements—opening a path for OSATs and legacy fabs to offer HBM-class packaging without EUV-scale capex. Attendees will leave with a framework for evaluating advanced packaging options through a sustainability lens (cost, energy, and materials per bit of bandwidth), and a view on how next-generation HRI technologies like LEM could decentralize AI packaging capacity while lowering the environmental footprint of the back end of line.

すべての業務プロセスにAIが導入された社会の実現を目指すRUTILEAのアプローチを紹介します