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Transformation of The Semiconductor Back-End Process!
The World of Fully Automated Back-End Processing that SATAS Aims For
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*Details will be provided in the FAQ.
In the semiconductor industry, there is a demand to address geopolitical risks, build stronger and more flexible supply chains, and advance and evolve packaging technologies. Automating the back-end process of semiconductors is an urgent necessity to achieve all of these simultaneously. SATAS contribute to the sustainable development of the industry by creating necessary industry standard specifications, developing equipment, and conducting pilot line verification to bring innovation to the semiconductor back-end process.
*Please note that the program may be subject to change.
概要文が入ります。
SATAS is a public-private research program with the Government of Japan to reimage and transform Assembly and Test manufacturing with innovative equipment, AMHS, smart manufacturing, and industry standards. SATAS is designed to enhance factory productivity, leading to domestic production, while enabling larger package sizes for AI era products. SATAS will develop, implement, and verify these technologies in an integrated pilot line located in Japan in 2027-2029.
SATAS aims not only to achieve full automation in semiconductor package assembly and testing processes but also to establish industry standards through the standardization of both physical and logical interfaces between the equipment necessary for such automation. In this part, I will introduce the vision and scope of standardization within SATAS.
概要文が入ります。
Current semiconductor back-end processes involve many areas where automation and standardization are difficult, resulting in production systems requiring human intervention. This creates challenges such as labor shortages and skill succession. Panel packages, used in advanced packaging like chiplet integration, remain particularly difficult to achieve unified automated production lines. To address these challenges, we are researching the full automation and standardization of chiplet integration packages manufactured at the panel level. In this presentation, we report on our current progress and future plans.
概要文が入ります。
概要文が入ります。