Dec.16_09:00_Strategic Materials Conference Japan 2025

China has rapidly advanced in semiconductor technology, now ranking second globally behind the United States, surpassing South Korea in key areas like AI chips, power semiconductors, and high-density storage . Despite U.S. export controls, China’s leading players have made significant breakthroughs. Foundries like SMIC have achieved stable 7nm production, while Yangtze Memory and CXMT are boosting domestic storage chip self-sufficiency. Chinese leading technology players are also making massive investments into AI and chips. Innovations like Chiplet packaging and carbon-based semiconductors further enhance performance while circumventing advanced node limitations . The emerging of leading China AI players has narrowed the gap with the U.S. Open-source pioneers like DeepSeek and Alibaba have demonstrated their commitment into AI training and reference. DeepSeek’s R1 model rivals OpenAI’s offerings, and China dominates in multimodal AI, achieving parity in text-to-image generation and nearing U.S. levels in video synthesis . Companies like ByteDance and Tencent leverage massive user data for refining models, while startups like Moonshot AI innovate in long-context processing . AI integration into industries—manufacturing, healthcare, and smart cities—showcases practical gains, such as predictive maintenance and AI-assisted diagnostics . Challenges persist, including EUV lithography dependency and high-end AI chip shortages . However, China’s "scenario-driven" approach, combining policy support, talent cultivation, and open-source collaboration, positions it to lead in scalable AI applications and next-gen semiconductors like quantum and photonic chips . This systematic progress underscores China’s transformative role in global tech.

The semiconductor market is showing a stable trend in terms of value due to the expansion of devices for generative AI in an uncertain external environment. On the capital investment side, China has leaded growth from 2022, and new fab in US is expected to increase from 2026 onwards. The market will maintain high level but on the other hand risks are accumulating. In this seminar, I would like to provide a bird's-eye view of the future semiconductor capital investment outlook and risks.

Silicon interposer technology has matured into a reliable and widely adopted solution for advanced semiconductor packaging. It enables high-density integration and efficient signal routing between chips. However, as chip sizes continue to grow, the traditional 12-inch round silicon wafers face limitations in terms of die yield and material utilization. The circular format often results in wasted silicon real estate, especially when accommodating rectangular device chips. To address this inefficiency, square or rectangular substrates—similar to glass panels—are being considered as a viable alternative to extend the lifecycle of silicon interposer technology. These formats align more closely with the shape of most semiconductor devices, potentially improving layout efficiency and reducing material waste. Despite their advantages, glass panels present several manufacturing challenges, including difficulties in through-via hole drilling, mechanical fragility, susceptibility to breakage, and risks of metal contamination. In contrast, silicon panel wafers offer a robust and compatible solution, mitigating many of these issues while supporting advanced packaging requirements. As packaging density increases, thermal management has become a critical concern. Efficient heat dissipation is essential to maintain device performance and reliability. To meet this need, various materials—particularly non-silicon and metallic compounds—have been explored. GlobalWafers Corporation (GWC) has successfully developed three types of silicon carbide (SiC) wafers: Single Crystal SiC, CVD Polycrystalline SiC, and Sintered Polycrystalline SiC. These materials are well-suited for thermal applications such as SiC interposers and heat sinks, offering superior thermal conductivity and mechanical strength.

Engineered substrates are essential foundation technology for enhancing semiconductor chip performance, which is indispensable for accelerating the AI era and cutting-edge computing. This presentation will introduce how Soitec, the world leader in engineered substrates, contributes to the evolution of AI infrastructure. Specifically, our Power-SOI substrates contribute to the automotive, industrial, and data center sectors by realizing power devices that enable power savings and high integration in AI infrastructure. Smart Photonics-SOI substrates provide a universal platform for high-speed, low-power data transfer for data centers. Furthermore, we are promoting the development of next-generation FD-SOI with a view toward the most advanced computing devices, supporting the evolution of the three major technologies: Computing, Connect, and Power.

In the development and mass production of leading edge semiconductors, semiconductor materials play a critically important role. This presentation discusses the significance of semiconductor materials for next-generation devices from the following perspectives: (1) Materials technologies required for 2nm/1.4nm generation advanced semiconductors (2) Materials challenges that are becoming bottlenecks in development and directions for their resolution (3) Collaborative approaches between Rapidus and materials suppliers (4) Initiatives and perspectives for achieving sustainability

High performance computing for AI has replaced smartphone and PC as the biggest driver for advanced logic processes. This presents new set of challenges. We will discuss several key areas that presents both challenges and opportunities for the semiconductor materials suppliers, including new transistor structure (GAA), new interconnect architecture (back-side power rail) and interconnect materials (Ru, Mo), performance improvement through new EUV resist (MOD based EUV dry and wet resist), advanced packaging materials, and new materials for thermal management. We will also discuss the ever-harder task of achieving high yield as node transition continues, and present new contamination control technologies as the key enabler for yield enhancement.

With continued scaling of logic devices to advanced nodes, post-CMP cleaning plays a critical role in defect control and yield improvement. This presentation will cover key trends in cleaning technologies, challenges such as material compatibility and defectivity, and outline solutions and strategies for next-generation logic manufacturing

As semiconductor technology continues to advance, improvements in back-end processes are becoming more important than ever. Among these, advanced packaging technologies are essential for achieving higher performance, greater functionality, and more compact integration in modern devices. This presentation will introduce the latest developments in advanced semiconductor packaging technologies.

With the recent spread of generative AI, the storage market is expected to continue growing, especially for inference applications. We are developing BiCS FLASH™ with competitive advantages to meet diversifying storage needs such as high performance, large capacity, and low power consumption. In addition to technology trends, we will share our prospects, including expectations for materials from device performance requirement.

This presentation will introduce the current status of Mitsui Chemicals' efforts in developing materials for next-generation advanced semiconductor packaging, as well as future prospects.

To meet growing demands in AI semiconductors, memory packaging technologies are advancing. Resonac has expanded its co-creation platform with materials and equipment makers to accelerate the development of advanced packaging, yielding notable results. This presentation outlines Resonac's roadmap for developing advanced materials for next-generation memory packaging.

EUV-CAR lithography is widely used for the high-volume manufacturing (HVM) of advanced semiconductor devices. Water-based rinse treatment following TMAH development is an essential process for achieving yield improvement. In this study, the role of rinse materials and the required performance in EUV-CAR, and performance evaluation methods will be presented.

The semiconductor supply chain is facing new challenges as the electronics industry changes in 2025. Suppliers must adapt to new geopolitical realities, shifting supply chains, and ever more challenging technology requirements. We will review some of the issues and developments.

The needs for data processing are increasing exponential due to expansions of applications, including but not limited to, LLM and cryptocurrencies. In this session, we will examine the market trends in Japan semiconductor material industries that enable lowering both latency and power-consumptions, which are vital to fulfil such rapidly growing needs.